The flip-flop will change its output only during the rising edge of the clock signal. The clock signal for the JK flip-flop is responsible for changing the state of the output. The reset button should be pulled up through a 1K resistor and when grounded will reset the flip-flop. That is the pin will held to ground when the button is not pressed and when the button is pressed the pin will be held to supply voltage. Input pins are pulled down to ground through a 1k resistor, this way we can avoid the pin in floating condition. The J and K pins are the input pins for the Flip-Flop and the Q and Q bar pins are the output pins. The below circuit shows a typical sample connection for the working of JK flip-flop This IC can be used in latching applications or can act as a small programmable memory for you project.Īs told earlier 74LS73 have two negative edge triggered JK flip flops, the IC is powered by +5V. J-K input is loaded into the master while the clock is high and transferred to the slave on the high to low transition. Meaning it has two JK flip flops inside it and each can be used individually based on our application. The 74LS73 is a dual in-line JK flip flop IC. Note: Complete Technical Details can be found at the 74ls73 datasheet give at the end of this page.Īlternatives JK Flip-Flop: 74LS76, 74LS107, 4027B Available in 14-pin PDIP, GDIP, PDSO packages.Operating temperature range = -55 to 125☌.Resets the flip flop by clearing its memory These pins must be provided with clock pulse for the flip flop The 74LS73 is a positive pulse triggered flip-flop. It contains two independent J-K flip-flops with individual J-K, clock and direct clear inputs.

7478 jk flip flop multisim